Electrical display devices

ABSTRACT

An addressing circuit arrangement for an electrical display device comprising a two-dimensional matrix of light-emitting elements which are connected at respective crosspoints formed by two groups of row and column conductors and each of which can be illuminated selectively by suitable energizing signals applied contemporaneously to the two conductors, one in each group, between which the element is connected. The arrangement includes, a circulation memory for storing character data in respect of a plurality of lines of characters to be displayed and for supplying in turn the character data for each line of characters serially character by character in a recurrent cycle, a character generator which is responsive to the supplied data for each character to produce a group of coded electrical signals that determine the discrete parts of the character to be displayed in the row of elements concerned, and a row store for storing in each fill period of each row period the several groups of coded electrical signals for the whole of the row of elements concerned.

United States Patent [191 Sharpless July 17, 1973 ELECTRICAL DISPLAY DEVICES [75] Inventor: Graham Trevor Sharpless, Burgess Hill, Sussex, England [73] Assignee: U.S. Philips Corporation, New York,

221 Filed: Mar. 16, 1972 2| App]. No.: 235,351

[30] Foreign Application Priority Data Primary ExaminerRaulfe B. Zache Attorney-Frank R. Trifari L INE scanner:

CIRCULATION "Em? KEYBOARD [57] ABSTRACT An addressing circuit arrangement for an electrical display device comprising a two-dimensional matrix of light-emitting elements which are connected at respective crosspoints formed by two groups of row and column conductors and each of which can be illuminated selectively by suitable energizing signals applied contemporaneously to the two conductors, one in each group, between which the element is connected. The arrangement includes, a circulation memory for storing character data in respect of a plurality of lines of characters to be displayed and for supplying in turn the character data for each line of characters serially character by character in a recurrent cycle, a character generator which is responsive to the supplied data for each character to produce a group of coded electrical signals that determine the discrete parts of the character to be displayed in the row of elements concerned, and a row store for storing in each fill period of each row period the several groups of coded electrical signals for the whole of the row of elements concerned.

12 Claims, 1 Drawing Figure DISPLAY PANEL Y COUNTER 17 COUNTER PAIENIEUJUL 1 TIM 3.147. 07 3 LINE DECODER SCANNER DISPLAY PANEL oscooaR DRIVERS coumens ozcoozn MONOSTABLE 12 CIRCULATlON Y COUNTER MEMORY COUNTER KEYBOARD 1 ELECTRICAL DISPLAY DEVICES This invention relates to addressing circuit an arrangement for an electrical display device comprising a two-dimensional matrix of light-emitting elements which are connected at respective crosspoints formed by two groups of row and column conductors and each of which can be illuminated selectively by suitable energizing signals applied contemporaneously to the two conductors, one in each group, between which the element is connected. The arrangement includes, a circulation memory for storing character data in respect of a plurality of lines of characters to be displayed and for supplying in turn the character data for each line of characters serially character by character in a recurrent cycle, a character generator which is responsive to the supplied data for each character to produce a group of coded electrical signal that determine the discrete parts of the charracter to be displayed in the row of elements concerned, and a row store for s toring in each fill period of each row period the several groups of coded electrical signals for the whole of the row of elements concerned.

Tabular data displays are increasing being used for read-out of computer information. For some applications e.g. desk-top computers, only small amounts of information (a few lines of characters) are needed at a time. For these applications, a c.r.t. display is bulky and not necessarily the cheapest way of displaying the information. Recent developments of glow discharge panels offer an attractive alternative solution.

An electrical display device comprising glow discharge cells comprises e.g. a small 5 X 7 cell matrix of glow discharge cells and is suitable for displying one alpha-numeric character. A plurality of similar small cell matrices can be used to form a composite panel of larger size suitable for displaying a relatively large number of alpha-numeric characters simultaneously. Unitary larger size panels comprising a two-dimensional matrix of glow dischrge cells and suitable f displaying a plurality of characters are also becoming available. Each character region of such large size panel can comprise 6 X 8 48 cells, of which X 7 35 are active cells for character formation and the remaining cells provide guard bands for spacing apart adjacent characters and adjacent lines of characters.

An addressing circuit arrangement for an electrical display device of the kind referred to is required to address the device with energizing signals appropriate for illuminating selectively the light-emitting elements of the device to provide a visual display of alpha-numeric characters. The selective energisation of the lightemitting elements to produce the visual display can be effected by addressing each row of elements in turn with energizing signals applied to the row conductors in a recurrent scanning cycle and by arranging that durin g the period that each row is being addressed, the columns of elements are addressed selectively with energizing signals applied to selected column conductors which pertain to those elements in the row that are to form discrete parts of the characters to be displayed, this addressing of the columns being determined by coded electrical signals that signify these discrete parts of the characters to be displayed. Thus, these elements, and only these elements are addressed with coincident energizing signals and are therefore illuminated. Assuming that a plurality of lines of characters, with each line containing a plurality of characters, are to be displayed and assuming that each line of characters extends over several rows (e.g. seven) of light-emitting elements then it will be appreciated that if the rows are addressed in turn in the scanning cycle, the characters in each line are built-up row-by-row, as a whole, and the lines of characters are built-up in succession. Thus, with a sufficiently fast scanning rate, the efi'ect will be the visual display of the plurality of lines of characters simultaneously. For a satisfactory display using this recurrent scanning cycle mode of operation, a field rate of at least 50 Hz is desirable in order to prevent flicker, that is, the matrix is scanned row-by-row sequentially 50 times per second. As an alternative to scanning the matrix row-by-row sequentially, the scanning may be performed in a pseudo-random fashion, in which the rows are addressed in turn in a predetermined recurrent pattern. This scanning cycle mode of operation (whether row sequential or non-sequential) will be referred to hereinafter as the line-dumping mode".

The words row" and column" are used, and will be so used hereinafter, solely to distinguish between the two groups of co-ordinate lines of light-emitting elements which form the two-dimensional matrix of an electrical disply device of the kind referred to. Thus, the elements of either of these groups can be termed row elements" with the elements of the other groups being termined colum element". The two groups of co-ordinate conductors which form the cross-points are correspondingly termed, row conductor and column conductors".

In an addressing circuit arrangement for an electrical display device of the kind referred to, the coded electrical signals that represent the characters to be displayed can be produced by the character generator in response to character data supplied to it from the circulation memory in which character data in respect of all the characters to be displayed is stored. Conveniently, the character generator is a read-only memory store containing the addresses of 64 different characters in the ASCl 1 code, each character address being identified by character data in the form of a 6-bit code supplied from the circulation memory, and each character address providing seven S-bit words. The character generator can be strobed to produce any one of the seven 5-bit words of a character which is identified by the relevant character data (45-bit code) supplied from the circulation memory. These 5-bit words are the coded electrical signals that represent the characters to be displayed. In order to energize selectively a whole row of elements, the row store is required to store the successive 5-bit words produced by the character generator until all the 5-bit words pertaining to a whole line of characters to be displayed have been produced. This storage operation takes place in what will be called a fill period (T!) at the beginning of the period (which will be called the row period Tr) in which the row of elements concerned is addressed. Therefore, the columns of elements of the matrix are addressed for a period Tr Tf to illuminate the row of elements. In order to achieve maximum brightness, the period Tr 7f should be as long as possible. Suitably, Tf can be chosen to be 20 percent of Tr (i.e. Tf= Tr/S).

Since the character generator can deal with only one character at a, time, the character data for a complete line of characters has to be supplied to its sequentially from the circulation memory. Furthermore, since the character generator produces only one -bit word at a time in respect of each character, the character data for a line of characters has to be supplied to the character generator seven times in order to display the character line. One possible way of achieving this would be to use an auxiliary circulation store into which the character data for a complete line of characters is fed from the circulation memory and to recirculate this character data seven times to supply the character generator in seven successive fill periods (1]). After a line of characters had been dealt with in this way, the auxiliary circulation store would be emptied and then fed with the character data for the next line of characters, and so on. Another possible way, which avoids the use of an auxiliary circulation store, would be to run the circulation memory at a sufficiently high speed such that all the character data for the several lines of characters is fed out in each fill period (7]) with the character data for the relevant line being gated to the character generator.

However, it has been found that each of these two possible ways of supplying character data from the circulation memory to the character generator requires a greater precision and speed of operation than can be realized using the relatively cheaper logic devices that are presently available. The present invention provides an improved, cheap addressing circuit arrangement.

An addressing circuit arrangement according to the present invention is characterized in that the cycle period of the circulation memory is different from the row period such that for a given order of storage of the character data for the several lines of characters in the circulation memory, the data for each line of characters is supplied in the fill period of every nth row period, where n is the number of lines of characters to be displayed.

An embodiment is characterized in that for a chosen percentage (e.g. percent) of the row period (Tr) to be occupied by the fill period (If), the character data for each line of characters occupies a period which is the same as the fill period in the cycle period of the circulation memory and this cycle period Tr/Tf n (Tf) provided that the ratio Tr/Tfis not equal to n and that there is no common factor of both Tr/Tf and n.

in order that the invention may be more fully understood reference will now be made by way of example to the accompanying drawing the single FIGURE of which shows a schematic diagram of an addressing circuit arrangment for an electrical display device of the kind referred to.

In the drawing, the addressing circuit arrangement is provided for a display panel I. This panel I is assumed to be a panel of gas discharge cells on which can be displayed a total of 64 characters arranged in four lines of 16 characters, using a standard 5 X 7 cell format for each character and allowing one cell column spacing between characters and two cell rows between lines of characters.

The panel 1 can consist essentially of two moulded glass-metal components, namely a plar body comprising a recessed cathode array and a window to which strip anodes are attached and are taken out through glass-to-metal seals at the ends of the panel 1. One anode strip is common to each (horizontal) row. Each (vertical) column of cathodes consists of one strip of metal passing through the body of the panel 1.

Any cell in the panel 1 may be ignited by applying a suitable voltage between the anode and cathode crossbars which intersect at the cell. A display can therefore be built up by addressing selected cells at a fast enough refresh rate to avoid flicker. For a given current per cell, the maximum brightness is achieved by row instead of point address. The abode cross-bars are addressed with a positive going pulse, while selected cathode cross-bars are simultaneouslly addressed, in parallel, with negative going pulses.

A resistance is needed in series with one of the crossbar electrodes to limit the glow discharge current. In practice, because of the scanning method adopted, this resistor is placed in series with each cathode cross-bar.

Each cell has characteristic ignition and maintaining voltages (V, and V,,,). For a panel 1, such as described above, there will be a spread in both V, and V,,,. The anode and cathode pulses must be selected so that addressed cells are successfully ignited while unaddressed cells remain off. For the line-dumping mode of operation, the voltage applied across an addressed cell, equal to the anode and cathode pulses plus a bias voltage, must ignite it. Also the bias plus only one pulse must be less than the minimum V, to prevent any unwanted cell from igniting.

The addressing circuit arrangement for the panel I comprises a 28-way scanner 2 for addressing the anode (row) cross-bars of the panel 1 with row energizing signals. This scanner 2 consists of a sub-matrix of 28 anode driver transistors arranged in a 4 X 7 matrix with their emitters connected to four lines 3 and their bases connected to seven lines 4. The lines 3 are connected via respective buffer stages (not shown) to a line decoder 5 which provides a recurrent cycle of four enable signals, and the lines 4 are connected via respective buffer stages (not shown) to a row decoder 6 which provides a recurrent cycle of seven enable signals. Each of these 1 1 buffer stages comprises a transistor invertor. A desired scanning sequence is determined by suitably wiring the line and row decoder lines 3 and 4 to the driver transistors (via the buffer stages). Since the character positions are fixed on the display panel I, the unused anode cross-bars may be ignored as far as the row scanning is concerned.

The active cell columns for character formation are addressed by 80 cathode driver transistors 7. Here again, since the character positions are fixed unused cathode cross-bars may be ignored. The cathode drivers 7 produce column energizing signals for addressing the cell columns under the control of an 80-bit row store 8. The row store 8 suitably comprises 80 latching bistables arranged in a 5 X 16 matrix, with five data input leads A to E from a character generator 9 and i6 enable inputs derived from a [6-way decoder 10.

A buffer (circulation) memory it holds character data to be displayed in the form of a 6-bit word per character, to define one of 64 different characters. The memory 11 can hold the character data for 64 characters. The character generator 9 produces a 5-bit output on leads A to E equivalent to a particular row ofa character, defined by a 6-bit input on leads 12 from the buffer memory 11. A counter 13, having a recurrent count of seven, determines in respect of which particular row of the 5-bit output on leads A to E pertains, in synchronism with the action of the row decoder 6 which is also driven from the counter 13. The buffer memory 11 comprises six 64-bit recirculating M.O.S.

shift registers. The character generator 9 is a M.().S. Read Only Memory.

Since a glow discharge display has negligible persistence of light output, a refresh rate of at least 50 Hz is necessary. To ensure minimum ignition delays with comparatively low supply voltages a refresh rate of up to 500 Hz can be used. For the reasons given below this implies a clock rate, for the buffer memory 11 and character generator 9 of about 1 MHz. This is within the maximum limit for available Read Only Memories.

A summary of possible clock rates etc. for the arrangement being described may be as given in the Table below.

TABLE I 4 X 6 CHARACTER ALPHA-NUMERlC DISPLAY Specification No. of active rows 28 No. of active columns 80 Field rate 500 Hz Row rate l4 kHz Row time 7| us Fill time [4 us Clock rate 1.] MHz Address time 57 us ON time 40 to 50 us Duty Cycle 1:40 to [:50

In operation of the addressing circuit arrangement the row store 8 is filled during the first l4 11S (20 percent see below) of the row period (Tr) leaving 57 415 for addressing the panel display via the cathode drivers 7. These drivers are blanked during the fill period (Tf) by the output from a counter 14, this output also being an enable input to counter 14 which controls the data output from the character generator 9 to the row store 8 and also the row decoder 6 and the decoder 10. This output from counter 14 is also an enable input to a counter 15 which controls the line decoder 5. Thus, an anode pulse is present for the whole of each row period Tr, but for each anode driver appears only once per field, that is, once per scanning cycle of the anode submatrix scanner 2. On the other hand, a complete column of lit cells requires the appropriate cathode driver of the drivers 7 to be on" continuously, except for the blanking period.

Since there is a finite delay time between addressing a cell and its ignition, the cell is alight for appreciably less than the row period Tr. The delay is typically ID to 15 S.

With regard to the timing of the buffer memory and row store cycles, the data recirculated in the buffer memory 11 is read out, 16 characters per row period Tr, during the row store fill period Tf. This data is organised character sequentially, with the first l6 characters defining the first line, the second l6 defining the second line and so on. At the start of each field period, of length 2ms, the first line of l6 characters is read out from the buffer memory ll and the first row of each character is produced by the character generator 9 under the control of the counter 13 and loaded into the row store 8. The counter 13 ensures correct synchronization between character generator row and disply row.

For the second row period the second line of l6 characters is read out from the buffer memory 11, while the anode sub-matrix scanner 2 addresses row 2 of character line 2, that is, eight active display rows further down the panel from row 1 of character line which was the row addressed in the first row period. The timing of the arrangement must therefore ensure that the correct data occurs at the correct time.

This mode of data access is the reason for the 20 percent fill period referred to earlier. The cycle lengths of the buffer memory 11 and row store 8 are respectively, 57 S and 71 #8. Every row period Tr, the buffer memory 11 goes through [.25 cycles so that a new line of 16 characters can be read. This phase-slip is such that for 4 row periods the data in the bufi'er memory 11 is recirculated 5 times. This is repeated 7 times per field.

The abode scanning sequence performed by the scanner 2 is determined by the above conditions. As mentioned, one row of each line of characters is addressed in turn. The seven rows of each line may be addressed in any sequence since the same counter 13 addresses both the scanner 2 and the character generator 9. In practice the row decoder 6 and line decoder 5 can be clocked together, as shown, so that each of seven capacitors coupling the row decoder 6 to the row buffers has only to be large enough for a 8 pulse instead of a 280 #8 pulse.

Data is inserted into the buffer memory 11 as 6-bit words and up-dated as required by means of a key board 16. The required position of a 6-bit word in the buffer memory 11 is determined by an X-counter l7 and a Y-counter 18 which together provide a count of 64 and feed the appropriate combination of count sig nals to a write-enable comparator 19. The latter is also receiving positional count signals from two further counters 20 and 21 which are synchronised with the recirculating operation of the arrangement. When coincidence exists between the two sets of count signals, the comparator 19 applies a "write"-enable pulse to the buffer memory 11 to cause it to store in the character position then obtaining the data presented to it from the keyboard 16.

The addressing circuit arrangement is driven l.l MHz clock pulses applied to terminals 22. The pulses are applied directly to the counter 20 and the outputs from this counter provide the synchronized operation of the arrangement via counters l4 and 21 and the decoder 10. The arrangement also includes a monostable 23 which is driven by the counters l3 and 15 and provides a reset pulse for the counters l5 and 21 for each field of the display. The character generator 9 and buffer memory 11 are driven directly by the l.lMl-lz clock pulses.

In order to underline the general idea of the invention some examples are given. Assume that n is the number of lines of characters to be displayed and a ratio P= Tr/Tf= 5. This value of P will be used in the following examples of different phase slips between the cycle period of the circulation memory I] and each row period over :1 row periods.

Consider first the described case where P (i.e. 5) is greater than n (i.e. P n). If, for example there are four lines of characters to be displayed, P n l (i.e. 5 4 l and the phase-slip is such that for 4 row periods the character data in the circulation memory I l is recirculated 5 times. Thus for every row period the circulation memory goes through 1.25 cycle periods and character data for a different line is supplied in 4 successive row periods. If there are eight lines of characters to be displayed, P= n 3 (i.e. 5 8 3) and the phase-slip is such that for 8 row periods the character data in the circulation memory I] is recirculated 5 times to supply character data for a different line in 8 successive row periods. For four lines of characters, the character data would be stored sequentially in the circulation memory 11, that is, in order: line 1, line 2, line 3, if the read-out from the circulation memory 11 is required in that order. For sequential read-out of the character data for eight lines of characters, the character data would be stored non-sequentially in the circulation memory in order: line 1, line 6, line 3, line 8, line 5, line 2, line 7, line 4.

Since the data for a character line is supplied every nth row period (in the fill period thereof), the rows of elements are required to be addressed with energizing signals applied to the row conductors in a sequence which selects a different row of elements of a character line for m appearances of the character data for that line from the circulation memory 11, where m is the number of rows of elements which make up a character line. In accordance with a feature of the invention, the required sequence can readily be provided by using the sub-matrix row scanner 2 comprising the twodimensional matrix of driver circuits which are ar ranged in :1 rows of m columns and each of which is rendered operable selectively to produce an element row energized signal in response to the coincidence thereat of two enable signals, one from the line decoder 5 which provides n enable signals in a recurrent cycle and the other from the row decoder 6 which provides m enable signals in a recurrent cycle, said line and row decoders being driven synchronously to produce their respective enable signals successively for successive row periods.

With the character data stored in the circulation memory 11 for sequential read-out, as aforesaid, Table II below gives the sequence that the row element energising signals would be produced for a four-line character display in which each character line consists of seven rows of elements and Table III below gives the sequence for an eight-line character display in which, again, each character line consists of seven rows of elements.

TABLE [I (4 X 7 enable signals) row (9) in the second row period. Line enable signal 4 and row enable signal 4 identify the fourth element row for the fourth line of characters, that is element row (25), in the fourth row period. For the fifth row period the line decoder starts a fresh cycle so that line enable signal 1 and row signal 5 identify the element row (5) for the first line of characters. Thus, in 28 row periods, 28 energizing signals are provided from the driver circuit in the sequence set forth in Table ll and exempli fied above. Exactly the same considerations apply in regard to Table III except that in this instance 56 energizing signals are provided in 56 row perids.

The use of the sub-matrix row scanner 2 in the manner set forth above permits connections to be made be tween the row conductors of a display matrix and the driver circuits without using cross-over wiring as would be required if the row energizing signals were supplied sequentially in row order from a shift register scanner. This facilitates the use of printed wiring for these connections.

What is claimed is:

1. An addressing circuit arrangement for an electrical display device, which arrangement includes, a circulation memory for storing character data of a plurality of lines for characters to be displayed and for supplying in turn the character data for each line of characters seri ally, character by character, in a recurrent cycle, a character generator connected to said circulation memory which is responsive to the supplied data for each character to produce a group of coded electrical signals that determine the discrete parts of the character to be displayed in a row of elements concerned, and a row store connected to said character generator for storing in each fill period of each row period the several groups of coded electrical signals for the whole of the row of elements concerned, a cycle period of the circulation memory being different from the row period such that for a given order of storage of the character data for the several lines of characters in the circulation memory, the data for each line of characters is supplied Row decoder unable signals 2 a t. a 1 I l 1(1) 9(2) 17(3) 25(4) 5(5) 13(6) 21(7) Elunltrlll. g 2 22(8) 2(9) 1000) 18(11) 26(12) 6(13) 14114) mw demde' "name sgmls a 15(15; 2306 am 11 1 19(1J) man 7m TABLE III (8 X 7 enable signals) Row decoder unable signals 7 f 2 i F.

l l(l) 9(2) 17(3) 115(4) 33(5) '1] (li) 4M7) 3; limit) 20!) ll)( IUJ lH(l l) 25(1)!) 3403) lZlH) 3 13(15) l'|l(lli) 3(17) llllfi) lilllll) 17(20) 36(15l) MH M Linn lilllllitl' vnnhlv signnls. 3M2: lug) mun) will) I row fi 2M2) 37(3") 'll'iflilj 5363!) M33) lllliii) ll (3) Illllillwl'. Ii 22(3) 341(37) iillflltl) lliliiil) M (40) li(4l) i l (42) Z lIiMIl) 23(41) ill (15) ililMli) 47(47) flfiMNj 7M9) it Hfl'illj lll(fil) il'JUiIl) 4mm) 'llilfifi) fiiillill) In Table II, line enable signal I and row enable signal 1 identify element row (I) of a display matrix in the first row period. This is the first element row for the first line of characters. Similarly, line enable signal 2 and row enable signal 2 identify the second element row for the second line of characters, that is element in the fill period of every nth row period, where n is the number of lines of characters to be displayed.

2. An addressing circuit arrangement as claimed in claim I, further comprising means connected to said character generator for controlling the character data such that for a chosen percentage of the row period (Tr) to be occupied by the fill period (Tf), the character data for each line of characters occupies a period which is the same as the fill period in the cycle period of the circulation memory, and this cycle period is Tr/Tf X n (Tf), provided that the ratio Tr/Tf is not equal to n, and that there is no common factor of both Tr/Tf and n.

3. An addressing circuit arrangement as claimed in claim 2, wherein said chosen percentage is 20 percent so that Tr/Tf= 5.

4. An addressing circuit arrangement as claimed in claim 2, wherein Tr/Tf n.

5. An addressing circuit arrangement as claimed in claim 2, wherein Tr/Tf n.

6. An addressing circuit arrangement as claimed in claim 3, wherein n 4, so that Tr/Tf= n l.

7. An addressing circuit arrangement as claimed in claim 3, wherein n 8, so that TrlTf= n 3.

8. An addressing circuit arrangement as claimed in claim 1, wherein the circuit arrangement further includes a sub-matrix row scanner for providing element row energizing signals in a required sequence, which sub-matrix row scanner comprises a two-dimensional matrix of driver circuits which are arranged in n rows of m columns, where m is the number of columns of elements which make up a character line, each of said driver circuits being operable selectively to produce an element row energizing signal in response to the coincidence there at of two enable signals, one from a line decoder which provides n enable signals in a recurrent cycle, and the other from a row decoder which provides m enable signals in a recurrent cycle, means for driving said line and row decoders synchronously to produce their respective enable signals successively for successive row periods, and a counter connected to said character generator and said row decoder for controlling the signals supplied from said character generator to said row store in synchronism with the enable signals supplied by said row decoder.

9. An addressing circuit arrangement as claimed in claim 8, wherein m 7,

10. An addressing circuit arrangement according to claim 8, further comprising an electrical display device connected to said row scanner responsive to the ener gized signals for displaying said characters.

11. The combination according to claim 10, wherein the electrical display device comprises a matrix of glow discharge cells.

12. The combination as claimed in claim ll, further comprising means disposed in said circuit for operating said display device at a field rate between 50 Hz and 500 Hz. 

1. An addressing circuit arrangement for an electrical display device, which arrangement includes, a circulation memory for storing character data of a plurality of lines for characters to be displayed and for supplying in turn the character data for each line of characters serially, character by character, in a recurrent cycle, a character generator connected to said circulation memory which is responsive to the supplied data for each character to produce a group of coded electrical signals that determine the discrete parts of the character to be displayed in a row of elements concerned, and a row store connected to said character generator for storing in each fill period of each row period the several groups of coded electrical signals for the whole of the row of elements concerned, a cycle period of the circulation memory being different from the row period such that for a given order of storage of the character data for the several lines of characters in the circulation memory, the data for each line of characters is supplied in the fill period of every nth row period, where n is the number of lines of characters to be displayed.
 2. An addressing circuit arrangement as claimed in claim 1, further comprising means connected to said character generator for controlling the character data such that for a chosen percentage of the row period (Tr) to be occupied by the fill period (Tf), the character data for each line of characters occupies a period which is the same as the fill period in the cycle period of the circulation memory, and this cycle period is Tr/Tf X n (Tf), provided that the ratio Tr/Tf is not equal to n, and that there is no common factor of both Tr/Tf and n.
 3. An addressing circuit arrangement as claimed in claim 2, wherein said chosen percentage is 20 percent so that Tr/Tf
 5. 4. An addressing circuit arrangement as claimed in claim 2, wherein Tr/Tf > n.
 5. An addressing circuit arrangement as claimed in claim 2, wherein Tr/Tf < n.
 6. An addressing circuit arrangement as claimed in claim 3, wherein n 4, so that Tr/Tf n +
 1. 7. An addressing circuit arrangement as claimed in claim 3, wherein n 8, so that Tr/Tf n -
 3. 8. An addressing circuit arrangement as claimed in claim 1, wherein the circuit arrangement further includes a sub-matrix row scanner for providing element row energizing signals in a required sequence, which sub-matrix row scanner comprises a two-dimensional matrix of driver circuits which are arranged in n rows of m columns, where m is the number of columns of elements which make up a character line, each of said driver circuits being operable selectively to produce an element row energizing signal in response to the coincidence there at of two enable signals, one from a line decoder which provides n enable signals in a recurrent cycle, and the other from a row decoder which provides m enable signals in a recurrent cycle, means for driving said line and row decoders synchronously to produce their respective enable signals successively for successive row periods, and a counter connected to said character generator and said row decoder for controlling the signals supplied from said character generator to said row store in synchronism with the enable signals supplied by said row decoder.
 9. An addressing circuit arrangement as claimed in claim 8, wherein m
 7. 10. An addressing circuit arrangement according to claim 8, further comprising an electrical display device connected to said row scanner responsive to the energized signals for displaying said characters.
 11. The combination according to claim 10, wherein the electrical display device comprises a matrix of glow discharge cells.
 12. The combination as claimed in claim 11, further comprising means disposed in said circuit for operating said display device at a field rate between 50 Hz and 500 Hz. 